1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to an internal voltage generator of a semiconductor integrated circuit.
2. Related Art
In recent years, an external voltage VDD, which is supplied to a semiconductor integrated circuit, in particular, a DRAM (Dynamic Random Access Memory), has been lowered. Accordingly, maximum suppression of a variation in internal power due to the variation in temperature is required. Furthermore, controlling the direction in which each internal power varies (positive or negative direction) to a desired direction is required.
Generally, in a basic memory cell structure of a DRAM, one transistor and one capacitor are connected to a word line and a bit line, as shown in FIG. 1. For the transistor used in the DRAM, an NMOS transistor is typically used, which is superior to a PMOS transistor in performance over size.
FIG. 2 illustrates a comparison between levels of voltages used in the DRAM. According to the comparison, the respective voltage levels are, in the order of largest to smallest, VPP, VDD, VCORE, VBLP & VCP, and VBB.
The voltage VDD is a voltage that is supplied from the exterior of the DRAM, and the voltages VPP, VCORE, VBLP & VCP, and VBB are generated by increasing or decreasing the voltage VDD. The voltage VPP is used in a word line driver, a data out driver, or the like to compensate for a loss of a threshold voltage VT of a transistor that is an element of a memory cell. The voltage VPP is generated by increasing the voltage VDD, and it is a larger voltage (largest value among internal voltages) than the voltage VCORE+the threshold value VT. The voltage VCORE is a voltage that corresponds to a cell voltage, that is, a data level of a cell. The voltage VBLP corresponds to a bit line precharge voltage, and the voltage VCP is a cell plate voltage and has the same level as the voltage VBLP. In addition, the voltage VBB corresponds to a substrate bias voltage, and it is applied to a bulk of the transistor with a negative value.
Hereinafter, an internal voltage generating circuit of a semiconductor integrated circuit will be described with reference to the accompanying drawings.
FIG. 3 is a circuit diagram illustrating an internal voltage generating circuit of a semiconductor integrated circuit according to the related art. FIG. 4 is a circuit diagram illustrating an internal structure of a substrate bias voltage detector shown in FIG. 3. FIG. 5 is a circuit diagram illustrating an internal structure of an elevated voltage detector shown in FIG. 3. FIG. 6 is a graph illustrating a variation in reference voltage in accordance with the related art. FIG. 7 is a graph illustrating an internal voltage requiring condition at a low temperature.
As shown in FIG. 3, the internal voltage generating circuit of the semiconductor integrated circuit according to the related art includes a reference voltage generating unit 10 that generates a base reference voltage VREF_BASE when an external voltage VDD increases to reach a predetermined level; a level shifter 11 that transforms the base reference voltage VREF_BASE into a first reference voltage VREF_C for generating a cell voltage and a substrate bias voltage, and a second reference voltage VREF_P for generating an elevated voltage, and outputs them; a cell voltage generating unit 12 that generates a cell voltage VCORE by using the first reference voltage VREF_C; a substrate bias voltage generating unit 13 that generates a substrate bias voltage VBB by using the first reference voltage VREF_C; and an elevated voltage generating unit 14 that generates an elevated voltage VPP by using the second reference voltage VREF_P.
The level shifter 11 has the structure of a differential comparator. In the level shifter 11, the base reference voltage VREF_BASE and a voltage VR divided by the resistors R1 and R2, are two input signals that are maintained at the same value through a feedback operation. The first reference voltage VREF_C is determined by the resistance ratio between the resistors R1 and R2. In addition, the second reference voltage VREF_P is generated by adjusting the resistance ratio, as in the first reference voltage VREF_C. For example, a plurality of resistors that have smaller resistance values than the resistors R1 and R2 are connected to one another, and the second reference voltage VREF_P is outputted from a node, which is selected among a plurality of nodes and outputs a desired voltage.
The cell voltage generating unit 12 includes a comparator 12-1 that has an inversion terminal “−” receiving the first reference voltage VREF_C, and a transistor 12-2 that has a gate receiving the output of the comparator 12-1, and outputs a cell voltage VCORE by transforming an external voltage VDD according to the gate voltage level while feeding the cell voltage back to a non-inversion terminal “+” of the comparator 12-1. This is the way in which the cell voltage generating unit 12 operates in order to maintain the level of the cell voltage VCORE at a predetermined value. The cell voltage generating unit 12 compares the first reference voltage VREF_C with the cell voltage VCORE, and turns on the transistor 12-2 when the cell voltage VCORE decreases to a voltage not more than the first reference voltage VREF_C, such that the cell voltage generating unit 12 is supplied with an external voltage VDD to increase the cell voltage VCORE. Further, when the cell voltage VCORE becomes a voltage not less than the first reference voltage VREF_C, the cell voltage generating unit 12 turns off the transistor 12-2, such that the cell voltage VCORE is no longer increased.
Furthermore, the substrate bias voltage generating unit 13 includes a comparator 13-1, a transistor 13-2, a substrate bias voltage detector 13-3 that detects the level of a voltage VCORE_BB outputted by the transistor 13-2 and outputs a substrate bias voltage pump enable signal, and a substrate bias voltage pump 13-4 that is driven by the substrate bias voltage pump enable signal and pumps the substrate bias voltage VBB. The connection between the comparator 13-1 and the transistor 13-2 is the same as the cell voltage generating unit 12. However, although the level of the voltage VCORE_BB is the same as the level of the cell voltage VCORE, since the amount of consumed current is smaller in the substrate bias voltage generating unit 13, the voltage VCORE_BB is different from the cell voltage VCORE in that the sizes of the comparator 13-1 and the transistor 13-2 in the substrate bias voltage generating unit 13 are smaller than those in the cell voltage generating unit 12.
In addition, the substrate bias voltage detector 13-3 has the structure shown in FIG. 4. If an absolute value of the substrate bias voltage VBB decreases, a resistance component of lower transistor 13-5 l increases. As a result, the substrate bias voltage detector 13-3 causes a potential at a node ‘DET’ to become a high level and thus causes a potential of a signal ‘BB_ENb1’ to become a low level. The signal ‘BB_ENb1’ is a signal that swings between the voltage VCORE_BB outputted by the transistor 13-2 and the ground voltage VSS. The level shifter 13-6 transforms the signal ‘BB_Enb1’ into a substrate bias voltage pump enable signal ‘BB_ENb2’ that swings between the external voltage VDD and the ground voltage VSS. When the signal ‘BB_ENb2’ becomes a low level, the substrate bias voltage pump 13-4 operates.
When the first reference voltage VREF_C is increases for any reason, the potential of the ‘DET’ node also increases. Due to this, in order to allow the potential at the ‘DET’ node to become a low level, the absolute value of the substrate bias voltage VBB should be further increased. As a result, the absolute value of the substrate bias voltage VBB is increased.
The elevated voltage generating unit 14 includes an elevated voltage detector 14-1 that outputs an elevated voltage pump enable signal by detecting the level of the second reference voltage VREF_P, and an elevated voltage pump 14-2 that is driven by the elevated voltage pump enable signal and pumps the elevated voltage VPP. The elevated voltage detector 14-1 has a structure as shown in FIG. 5. That is, a voltage at an ‘X node’ and a second reference voltage VREF_P are inputted to two input terminals of the differential comparator (transistors 14-3, 14-4). The ‘X node’ corresponds to a node at which a resistance is distributed such that it has the same potential as the second reference voltage VREF_P when the elevated voltage VPP is a target value. Therefore, when the elevated voltage VPP becomes lower than the target value, since the voltage at the ‘X node’ also becomes lower than the second reference voltage VREF_P, an elevated voltage pump enable signal ‘PP_EN’ becomes a high level through the operation of the comparator, such that the elevated voltage pump 14-2 pumps the elevated voltage VPP.
In the case in which the second reference voltage VREF_P for generating an elevated voltage increases for any reason, in the elevated voltage detector 14-1, the elevated voltage VPP becomes larger than an original target value, which causes the level of the elevated voltage pump enable signal ‘PP_EN’ to become a low level. As a result, the elevated voltage VPP is increased.
At this time, as shown in FIG. 6, when the base reference voltage VREF_BASE varies, the second reference voltage VREF_P outputted by the level shifter 11 also varies. That is, when the base reference voltage VREF_BASE decreases, the second reference voltage VREF_P for generating the elevated voltage also decreases.
In the meantime, in low temperature conditions (at a cold temperature, for example, −10° C.), the threshold value VTN of the NMOS transistor increases even when the elevated voltage VPP, the cell voltage VCORE, and the substrate bias voltage VBB are constant, which results in lowering the current drivability of the NMOS transistor. Therefore, as shown in FIG. 7, in low temperature conditions, increasing the elevated voltage VPP and the cell voltage VCORE and decreasing the substrate bias voltage VBB (hereinafter, the decrease of the substrate bias voltage VBB refers to the reduction of the absolute value) are effective in normal operation of the semiconductor integrated circuit.
However, according to the related art, the corresponding internal voltages are generated by using the reference voltage generated from the source without considering variations according to the temperature condition. Therefore, if the corresponding internal voltages, that is, the elevated voltage VPP and the cell voltage VCORE are increased by increasing the reference voltages VREF_P and VREF_C in low temperature conditions, the substrate bias voltage VBB that should be lower than the corresponding level or maintained at the corresponding level also increases (hereinafter, the increase of the substrate bias voltage VBB refers to the increase of the absolute value). As a result, the semiconductor integrated circuit element experiences a decrease in performance.